Flash Memory: Electrons Trapped on a Floating Gate for Ten Years

Anatomy of a Cell: A MOSFET With a Sealed Pocket for Charge

An ordinary n-channel MOSFET turns on when its gate voltage exceeds a threshold voltage, V_t. A flash cell adds a second gate that no wire touches. From the silicon upward the stack is: the p-type channel; a tunnel oxide of SiO₂ only ~7–10 nm thick; the floating gate, a slab of doped polysilicon; a thicker oxide-nitride-oxide (ONO) layer; and the control gate, the word line the chip actually drives.

The floating gate is wrapped completely in insulator. To an electron inside it, the SiO₂ boundary is a wall ~3.1 eV high, the Si–SiO₂ energy barrier, about 120 times the ~0.026 eV thermal energy of an electron at room temperature. Stored electrons can leave only by tunneling through the oxide or by being kicked over it.

Charge on the floating gate screens the channel from the control gate, so the control gate must be driven higher before the cell turns on. The threshold moves by ΔV_t = −Q/C_CG, where Q is the stored (negative) charge and C_CG the capacitance between control gate and floating gate. In NAND flash the cells are wired in series strings, 32 to 64 cells long in late planar chips and one cell per layer in 3D stacks, sharing a single bit-line contact. That sharing lets a NAND cell approach the ~4F² minimum area, where F is the smallest drawn feature.

Programming: Fowler-Nordheim Tunneling in Verified Steps

To program a NAND cell, the chip holds its channel at 0 V and pulses the control gate high. The floating gate takes up a fraction of that voltage set by the coupling ratio α = C_CG/C_total, ~0.6 in typical cells: V_FG = α·V_CG + Q/C_total.

At ~10 MV/cm across the tunnel oxide, the rectangular 3.1 eV barrier tilts into a thin triangle, and channel electrons tunnel through its tip onto the floating gate. This is Fowler-Nordheim tunneling, J = A·E²·exp(−B/E), with B ≈ 240 MV/cm and A ≈ 1.2×10⁻⁶ A/V² for Si/SiO₂.

Worked example. Take α = 0.6, a 9 nm tunnel oxide and an uncharged cell. A first pulse of ~15 V gives V_FG ≈ 0.6 × 15 = 9 V, so E ≈ 9 V ÷ 9 nm = 10 MV/cm. Then B/E = 24, exp(−24) ≈ 3.8×10⁻¹¹, and J ≈ 1.2×10⁻⁶ × (10⁷ V/cm)² × 3.8×10⁻¹¹ ≈ 4.5 mA/cm². At 8 MV/cm, B/E = 30 and J falls to ~7 µA/cm², roughly 600 times less.

Controllers use incremental step pulse programming (ISPP): the gate is stepped from ~15 V toward ~20 V in ~0.2–0.5 V increments, verifying after each pulse and locking out cells that reach target. It is self-limiting: at 20 V with no stored charge, V_FG would be 12 V and the field 13 MV/cm, but the electrons already collected pull the floating gate down. Holding ~10 MV/cm at 20 V requires Q/C_total = −3 V, which the control gate sees as ΔV_t = 3 V ÷ 0.6 = 5 V, exactly the 5 V the pulse rose. Each step raises V_t by about one step, so step size sets placement precision. Cells that must stay erased are inhibited by floating their channels, which the word lines boost to several volts.

Reading, Erasing and Packing Bits Into Voltage Levels

To read an SLC NAND cell, the chip puts ~0 V on the selected word line and a pass voltage of ~5–6 V on the other word lines in the string, turning those cells on whatever they store. An erased cell has V_t below 0 V, so it conducts and the precharged bit line discharges: logic 1. A programmed cell, with V_t pushed to roughly +1 to +3 V, stays off: logic 0. An SLC page read takes on the order of 25 µs.

How much charge is involved? With an illustrative C_CG ≈ 30 aF (3×10⁻¹⁷ F, plausible for a planar cell near the 50 nm node), a 3 V shift needs Q = −3 V × 3×10⁻¹⁷ F = −9×10⁻¹⁷ C, about 560 electrons. By the ~15 nm node where planar NAND ended, a handful of electrons measurably moved V_t.

Erase reverses the field. A block's word lines are held at 0 V while the p-well beneath rises to ~20 V, so electrons tunnel out of every floating gate in the block at once. The all-at-once erase reminded Toshiba engineer Shoji Ariizumi of a camera flash, and he suggested the name. Block erase also forces SSDs to copy still-valid pages before reusing a block: garbage collection.

Multi-level cells program intermediate thresholds. MLC stores 2 bits as 4 threshold levels, TLC 3 bits as 8, and QLC stores 4 bits as 16 threshold-voltage levels, read against 15 reference voltages. In a ~6 V window, sixteen states get only ~0.4 V apiece, guard bands included, so QLC needs finer ISPP steps (slower writes) and stronger error correction, and suffers most from drift.

Why the Charge Stays for Ten Years, and How Flash Wears Out

Stored electrons put their own field across the tunnel oxide: in the example above, −3 V across 9 nm, or ~3.3 MV/cm. At that field B/E ≈ 72, and the Fowler-Nordheim relation predicts a current about 10²² times smaller than at 10 MV/cm, so small that a 100 nm × 100 nm cell would take tens of millions of years to lose one electron that way. That steep field dependence is why datasheets can quote ~10 years retention.

Real cells leak by other routes. Every program/erase cycle drives electrons through the oxide at high field, breaking bonds and creating oxide traps. Trapped charge narrows the gap between states, and chains of traps open trap-assisted tunneling paths (stress-induced leakage current, SILC) that let charge escape at ordinary fields. Because polysilicon conducts, one leaky spot can drain the entire floating gate, and heat speeds all of it. This damage sets endurance at SLC ~100,000 program/erase cycles; TLC ~1,000–3,000, with QLC commonly lower. Worn cells also retain data for far less than a decade.

• Read disturb: the pass voltage on unselected cells weakly programs them, so a block read many thousands of times must be rewritten.
• Cell-to-cell coupling (the Yupin effect): charge on one floating gate shifts the apparent V_t of the next, worse with every shrink.

These limits pushed the industry toward charge-trap storage. Samsung's 24-layer V-NAND of 2013, and most 3D NAND since, holds electrons in discrete traps in a silicon-nitride film around a vertical polysilicon channel. Nitride is an insulator, so a defect drains only nearby charge, not the whole cell, though charge can spread sideways along the film. Intel's 3D NAND, now made by Solidigm, kept a floating gate.

Specifying and Testing: Endurance, Retention Bakes and Error Correction

Makers cycle samples to rated endurance and then bake them, following JEDEC methods such as JESD22-A117 within the JESD47 qualification framework. Charge loss is thermally activated, so an Arrhenius model converts oven hours into field years: AF = exp[(E_a/k)(1/T_use − 1/T_bake)].

Worked example. Assume E_a = 1.1 eV, a common assumption for intrinsic charge loss, with k = 8.617×10⁻⁵ eV/K, use at 55 °C (328 K) and a bake at 125 °C (398 K). Then 1/328 − 1/398 ≈ 5.36×10⁻⁴ K⁻¹, E_a/k ≈ 12,770 K, and AF ≈ exp(6.84) ≈ 930. Ten years (≈87,700 hours) at 55 °C is modeled by roughly 94 hours at 125 °C. The result hinges on E_a: at 0.6 eV the factor drops to ~40, and the same bake stands in for only about five months.

At drive level, JEDEC JESD218 defines SSD endurance ratings. After writing its rated terabytes written (TBW), a client SSD must still retain data for 1 year powered off at 30 °C, and an enterprise SSD for 3 months at 40 °C, with an uncorrectable bit error rate no worse than 10⁻¹⁵ or 10⁻¹⁶ respectively. JESD219 defines the workloads behind TBW.

The controller makes raw cells meet those numbers. LDPC error correction fixes bit errors, read retry follows drifting distributions, and wear leveling spreads writes across blocks. A typical 1 TB TLC drive rated for ~600 TBW rewrites its capacity 600 times; with write amplification of 1.5–3×, that is ~900–1,800 cycles per block, inside TLC's ~1,000–3,000 budget.

From Bell Labs to 3D NAND: History and Real-World Failures

The floating-gate transistor was proposed in 1967 by Dawon Kahng and Simon Sze at Bell Labs. In 1971 Dov Frohman at Intel turned the idea into the EPROM, charged by hot electrons and erased by ultraviolet light shone through a quartz window. EEPROMs followed around 1980, erasing electrically through thin oxide but needing an extra transistor per bit.

Fujio Masuoka at Toshiba presented flash memory at IEDM in 1984 (the NOR type) and NAND flash in 1987. Intel shipped the first commercial NOR flash, a 256 kbit chip, in 1988, and its 1997 StrataFlash was the first commercial multi-level-cell flash. Samsung began mass-producing 24-layer V-NAND in 2013; commercial stacks passed 200 layers in 2022.

• Samsung 840 EVO (2014): old files on this early TLC SSD read far more slowly because threshold drift forced repeated read retries; Samsung shipped a tool that rewrote the data, then background-refresh firmware.
• Tesla eMMC recall (2021): Tesla recalled about 135,000 Model S and Model X cars after NHTSA found that the 8 GB eMMC flash in their media control unit wore out from constant logging, which could knock out the rear-view camera image and defogger controls.
• The 2015 retention scare: slides from a JEDEC presentation on JESD218 were misreported as proof that SSDs lose data within about a week unpowered. The figures described drives already worn to their rated endurance and stored hot.

Not DRAM, Not NOR: How Flash Differs From Its Look-Alikes

DRAM also stores a bit as charge, but on a capacitor of roughly 10 fF behind one access transistor, with no sealed barrier. Its leakiest cells lose their charge in a fraction of a second, so JEDEC DDR standards require refresh every ~64 ms (32 ms when hot). DRAM is fast and wear-free but volatile.

NOR flash uses the same floating-gate cell but wires each cell in parallel to the bit line, giving fast random reads so a microcontroller can run code directly from it. It programs by channel hot-electron injection, not tunneling: with ~9–10 V on the gate and ~4–5 V on the drain, electrons accelerating along the channel gain enough energy to clear the 3.1 eV barrier outright. That costs hundreds of µA per cell and a bigger cell (~10F² versus ~4F² for NAND), so NOR holds megabytes of boot code while NAND holds terabytes of data. Both erase by Fowler-Nordheim tunneling.

• EEPROM erases byte by byte, at the cost of extra transistors per bit.
• Hard disk drives store bits as magnetized grains, which writing does not wear out.
• Flash ADCs share only the name, which there means every comparator converts at once.

A common myth is that reading wears flash out. Reads cause disturb, which the controller clears by rewriting data; what damages the tunnel oxide is program/erase cycling.

Flash memory compared with the memories it is most often confused with

Memory	How a bit is stored	Without power	Endurance and upkeep
Planar NAND flash (floating gate)	Electrons tunneled onto an insulated polysilicon gate; cells wired in series strings	Retains data ~10 years when fresh	SLC ~100,000 program/erase cycles; erased a whole block at a time
3D NAND (charge trap)	Electrons held in discrete traps in a silicon-nitride film around a vertical channel	Non-volatile; retention falls with wear and heat	TLC ~1,000–3,000 cycles; QLC lower; needs strong ECC
NOR flash	Same floating-gate cell, wired in parallel; programmed by channel hot-electron injection	Non-volatile	~100,000 cycles per erase sector; fast random reads for code
DRAM	Charge on a ~10 fF capacitor behind one access transistor	Volatile; the leakiest cells lose their charge in under a second	No practical wear-out; refreshed every ~64 ms
EPROM	Floating gate charged by hot electrons	Non-volatile	Whole chip erased only by ultraviolet light through a quartz window
Hard disk drive	Magnetization direction of grains on a spinning platter	Non-volatile	Writing does not wear the medium; heads and motor wear mechanically