Space Vector Modulation: Squeezing 15% More Voltage Out of the Same DC Bus

Eight States, Six Directions: The Inverter as a Space Vector

A two-level three-phase voltage-source inverter has three half-bridges. Each leg connects its output to either the positive rail (state 1) or the negative rail (state 0), so the inverter has exactly 2³ = 8 switching states. Six of them (100, 110, 010, 011, 001, 101) produce nonzero line-to-line voltage; the two 'null' states (000 and 111) short all three phases to the same rail and produce zero output.

The insight of SVM is to map each state to a space vector using the Clarke transform, collapsing the three phase voltages (v_a, v_b, v_c) onto a single stationary complex plane (the α–β plane):

• V_ref = ⅔·(v_a + v_b·e^{j2π/3} + v_c·e^{j4π/3}) — the ⅔ scaling makes the vector magnitude equal the peak phase voltage.
• The six active states become six vectors of magnitude 2V_dc/3, spaced exactly 60° apart, forming a regular hexagon.
• The two null states both sit at the origin — zero magnitude.

A desired sinusoidal three-phase set of voltages is, in this plane, simply a rotating vector V_ref of constant magnitude tracing a circle at angular speed ω = 2πf. The inverter's job reduces to one question, asked ~10,000 times a second: 'I can only point in six fixed directions plus zero — how do I fake pointing here?'

Volt-Second Balancing: How You Fake Any Direction

You fake an arbitrary V_ref by time-sharing between the two adjacent active vectors that bracket it, then padding the rest of the switching period with the null vectors. Over one switching period T_s (typically 50–200 µs), the applied volt-seconds must equal the commanded volt-seconds — the volt-second balance that is the heart of all PWM:

• V_ref·T_s = V₁·T_a + V₂·T_b + V₀·T₀, with the dwell times constrained by T_a + T_b + T₀ = T_s.

If V_ref lies in Sector I (between V₁ at 0° and V₂ at 60°) at angle θ, solving the geometry gives the closed-form dwell times:

• T_a = T_s · m · sin(60° − θ)
• T_b = T_s · m · sin(θ)
• T₀ = T_s − T_a − T_b (split between the 000 and 111 null states)

where the modulation index m = √3·|V_ref|/V_dc. As long as T_a + T_b ≤ T_s, the inverter reproduces V_ref exactly on average. The remaining time T₀ is 'free' — it does no useful volt-second work, which is precisely the slack SVM exploits. In other sectors the same formulas apply after subtracting the sector offset (θ mapped into 0–60°), so a single set of equations plus a sector index (1–6) covers the whole hexagon.

Where the Extra 15.5% Comes From

The famous SVM voltage bonus is not magic — it is a consequence of how the null time is placed. In SPWM, the peak phase voltage that keeps the output linear is capped at V_dc/2, because each leg's duty cycle must stay between 0 and 1 and the references are pure sinusoids. The linear circle inscribed in the SVM hexagon, however, reaches all the way to the midpoint of each hexagon side, whose radius is:

• |V_ref|_max = (2V_dc/3)·cos(30°) = V_dc/√3 ≈ 0.577·V_dc

Compared to SPWM's V_dc/2 = 0.5·V_dc, that is a ratio of 2/√3 ≈ 1.1547 — the canonical 15.5% improvement. Push past this radius and V_ref exits the inscribed circle into the hexagon corners: the inverter saturates (overmodulation), the output distorts, and low-order harmonics appear.

Mathematically, SVM is equivalent to SPWM with 1/6-amplitude third-harmonic injection. Adding a triplen (3rd-harmonic) common-mode term to all three references flattens their peaks without changing the line-to-line voltage (triplens cancel in the line-line difference), buying headroom. SVM achieves the identical result geometrically by centering the null time symmetrically — the common-mode component emerges automatically. This is why an EV inverter on an 800 V bus delivers ≈462 V_peak per phase (327 V phase RMS, 566 V line-line RMS) instead of 400 V_peak: more torque and higher base speed from the same battery.

The Symmetric Seven-Segment Sequence

Knowing the dwell times isn't enough; the order in which you apply the states sets the harmonic quality and switching loss. The industry-standard symmetric seven-segment sequence arranges each T_s so that only one leg switches at a time and the pattern is a mirror image about the period center. In Sector I:

• 000 → 100 → 110 → 111 → 110 → 100 → 000, with the null time split half at 000 and half at 111 (T₀/2 each end, then the center).

Two payoffs fall out of this arrangement:

• Minimum switching count: exactly one device toggles per segment boundary. Over a full period each of the three legs switches once up and once down — six commutations, the theoretical minimum for two active + two null vectors.
• Lowest current ripple: the symmetric placement centers the active pulses within the period, which pushes the dominant voltage harmonics up to twice the switching frequency (2·f_sw) and its sidebands, well above the motor's electrical fundamental. Higher, cleaner ripple frequency means a smaller, cheaper DC-link capacitor and less motor heating.

Splitting the null time equally between 000 and 111 is what gives this continuous sequence its low ripple, though it costs the same six commutations per period as center-aligned SPWM. The ≈33% switching-loss saving comes instead from the opposite choice — discontinuous PWM, which dumps all the null time into a single state so one leg is clamped to a rail for a 60–120° span and skips a third of its commutations, at the price of higher current ripple.

Sizing the Real Inverter: Frequency, Dead Time, and Ripple

SVM lives inside real silicon, and three numbers dominate the design trade space.

• Switching frequency f_sw: Higher f_sw shrinks current ripple (ΔI ∝ V_dc/(L·f_sw)) and pushes acoustic noise above 20 kHz, but switching loss scales as P_sw ≈ ½·V_dc·I·(t_on + t_off)·f_sw. Silicon IGBTs live at 2–20 kHz; SiC MOSFETs, with 5–10× lower switching energy, run 20–100 kHz. A 100 kW traction inverter at 10 kHz commonly dissipates 1–2 kW in the switches alone.
• Dead time t_d: To stop shoot-through, both devices in a leg are off for a blanking interval of 0.5–3 µs (IGBT) or 50–500 ns (SiC). This directly corrupts the volt-second balance: the lost/gained volt-seconds per edge are ±V_dc·t_d, producing a duty error of t_d/T_s. At 10 kHz with t_d = 2 µs, that's a 2% distortion per commutation — the leading cause of low-speed torque ripple and 5th/7th-harmonic currents. Good drives run dead-time compensation based on the sign of phase current.
• Minimum pulse width: When T_a or T_b shrinks below the driver's minimum on-time (~1–2 µs) near the sector edges or at low modulation, pulses get dropped, injecting error. This sets a practical f_sw ceiling for a given gate driver.

A worked ripple estimate: a motor phase inductance L = 200 µH on a V_dc = 700 V bus at f_sw = 10 kHz sees peak ripple current on the order of ΔI ≈ V_dc·D(1−D)/(L·f_sw) ≈ (700·0.25)/(200µ·10k) ≈ 87 A pk-pk at 50% duty — which is why traction motors want higher inductance or SiC-enabled higher f_sw.

Where SVM Runs: FOC, Grid-Tie, and the Overmodulation Edge

SVM is almost never the whole controller — it is the final output stage that takes a commanded voltage vector and turns it into gate pulses. In an EV or industrial drive, the chain is: current sensors → Clarke/Park transforms → PI current loops in the rotating d-q frame → inverse Park → SVM → gate driver → IGBT/SiC bridge. This is Field-Oriented Control (FOC), and SVM is the actuator that FOC's voltage command flows through. The same block appears in:

• EV traction inverters (Tesla, Lucid, all modern BEVs): SVM's 15.5% bonus directly raises peak power and field-weakening range from a fixed battery.
• Grid-tie and PV inverters: SVM synthesizes the grid-frequency voltage vector for active/reactive power control; the higher DC-bus utilization lets a lower bus meet grid voltage with margin.
• Servo drives and BLDC/PMSM controllers: smooth low-ripple torque for robotics and CNC.

Beyond the linear circle, drives deliberately enter overmodulation to extract the last torque. Mode I clips V_ref to the hexagon boundary (fundamental grows to ~1.05× the linear limit with modest 5th/7th harmonics); Mode II holds V_ref at the six corner vectors longer, and at the extreme the inverter degenerates to six-step operation — full square-wave, delivering the absolute ceiling of 2V_dc/π ≈ 0.637·V_dc peak fundamental but with heavy harmonics. Field-weakening EV drives ride this edge at high speed on purpose.

Failure Modes, Limits, and Best Practice

SVM is robust but has sharp failure edges that show up as torque ripple, EMI, or blown legs.

• Shoot-through: too little dead time and both leg devices conduct simultaneously — a bus-to-ground short that destroys the module in microseconds. Always size t_d to the device's turn-off delay plus tail-current time, with margin.
• Common-mode voltage and bearing currents: the null-state placement creates a common-mode voltage stepping ±V_dc/2 at f_sw. Through parasitic capacitance this drives bearing discharge currents that pit races (EDM-like fluting) and radiates conducted EMI. Mitigations: common-mode chokes, shaft grounding rings, insulated bearings, or reduced-common-mode SVM variants that avoid the 111/000 pairing.
• Overmodulation harmonics: pushing past the inscribed circle without proper mode-I/II handling injects 5th and 7th harmonics that cause 6th-harmonic torque pulsation — audible growl and mechanical fatigue.
• Timing/latency: SVM math (sector ID, dwell times, sequence) must complete every T_s. At 20 kHz that's a 50 µs deadline; missed updates produce glitches. Hardware timers with center-aligned PWM and double-buffered compare registers are standard practice so the new duties load exactly at the period boundary.
• DC-link ripple: the pulsating draw stresses the bus capacitor; size it for the RMS ripple current, which peaks near m ≈ 0.6–0.9 and can reach 50–60% of the phase current RMS.

Best practice: center-aligned symmetric seven-segment sequencing, sign-of-current dead-time compensation, and a modulation-index limiter that cleanly transitions into a defined overmodulation strategy rather than letting V_ref clip unmanaged.

SVM vs conventional sinusoidal PWM (SPWM) on an identical two-level inverter with bus voltage V_dc

Metric	Sine-Triangle PWM (SPWM)	Space Vector Modulation (SVM)
Max peak phase voltage (linear)	V_dc/2	V_dc/√3 (+15.5%)
Max line-to-line RMS	0.612·V_dc	0.707·V_dc
Modulation index ceiling m	1.0	1.1547 (2/√3)
Effective harmonic method	None (fundamental only)	Implicit 1/6 third-harmonic injection
Switching loss / cycle	Baseline	Same commutation count (≈33% lower only in discontinuous variants)
Implementation	3 comparators, trivial	Sector logic + timing math, DSP/FPGA