Charge Pumps: Building Higher Voltage From Nothing But Capacitors and Switches

The core trick: parallel-charge, series-discharge

A charge pump exploits one fact of circuit theory: voltage adds in series, and a capacitor holds its voltage when you move it around the circuit. In the simplest form — the voltage doubler — a flying capacitor C_fly is first connected across the input so it charges to V_in. Then switches flip: its bottom plate is lifted to V_in while its top plate, still holding V_in across the cap, is connected to the output. The output node now sees V_in (from the lifted plate) + V_in (across the capacitor) = 2·V_in. Charge sloshes into a reservoir capacitor C_out, which smooths the pulsed delivery into a DC rail.

Stack this operation and the gains multiply. In the classic Dickson charge pump, a chain of N flying capacitors is driven by two non-overlapping clock phases (φ and φ̄, typically at V_in amplitude). On each clock edge, charge ratchets one stage down the chain, and every stage adds one clock-amplitude worth of voltage on top of the DC that has already accumulated. Ideally, N pumping stages plus the input give:

• V_out(ideal) = (N + 1)·V_in − N·V_diode for the original diode-coupled Dickson, where V_diode is the drop of each rectifying element (≈0.3–0.7 V).
• With MOSFET switches used as synchronous rectifiers, V_diode → I_out·R_on and the loss term collapses, letting modern pumps approach the ideal (N+1)× multiple.

The 19th-century ancestor is the Cockcroft-Walton multiplier, the diode-capacitor ladder rated for ~800 kV whose accelerated protons first split the lithium nucleus in 1932 (the disintegration was seen at a few hundred kV) — still used today for CRT anodes, X-ray tubes, and electrostatic precipitators.

The output-resistance model — why the rail sags

The single most important design equation is that a charge pump is not an ideal (N+1)× source. It is that source in series with an effective output resistance R_out. The loaded output is:

V_out = (N + 1)·V_in − I_out·R_out

and R_out has two limiting regimes governed by the ratio of clock period to the RC settling time of each pumping event:

• Slow-switching limit (SSL): when the flying cap fully settles each cycle, transfer is charge-quantized. Each cycle moves ΔQ = C_fly·ΔV, so R_out ≈ 1/(f·C_fly) per stage. This is the dominant regime for most designs and it is astonishingly simple: double the frequency or double the capacitance and you halve the output impedance.
• Fast-switching limit (FSL): when the switches, not the caps, throttle the flow, R_out is set by on-resistance and duty: R_out ≈ 2·R_on·D_factor, independent of frequency.

The real R_out is roughly the RMS combination, R_out ≈ √(R_SSL² + R_FSL²). A quick example: at f = 1 MHz with C_fly = 1 µF, the SSL term is 1/(10⁶·10⁻⁶) = 1 Ω. Draw 100 mA and you lose I·R = 100 mV of your step-up — plus another I·R across every switch. This is why datasheet plots of V_out vs. I_out are straight sagging lines, and why the pump is best matched to the load current it was sized for.

Efficiency: the fundamental capacitor-charging tax

Charge pumps carry an unavoidable thermodynamic penalty that inductive converters do not. When you connect a capacitor charged to V₁ onto one at V₂ through any resistance, the energy dissipated is ½·C·(V₁ − V₂)² — completely independent of the resistance value. You always pay it. This makes the ideal efficiency of a switched-cap converter a hard function of how far the output is from the topology's natural conversion ratio:

• η_max ≈ V_out / (N_ratio · V_in). A 2× doubler feeding an output that is only 1.6·V_in wastes 1 − 1.6/2 = 20% as pure conduction loss, no matter how good your silicon is.
• This is why practical pumps use multiple selectable ratios (½×, ⅔×, 1×, 3/2×, 2×). The controller hops between ratios to keep V_out just under the nearest ideal multiple, keeping efficiency high across a wide V_in — exactly how a modern fractional charge pump in a phone reaches 90%+ across the Li-ion 3.0–4.4 V window.

The other loss buckets: (1) gate-drive / dynamic loss = C_gate·V²·f, which grows with frequency and pushes back against the R_out benefit of clocking faster; (2) reversion / redistribution loss from parasitic bottom-plate capacitance C_par, typically 1–10% of C_fly, charged and dumped every cycle. There is a sweet-spot frequency where conduction loss (falling with f) and switching loss (rising with f) cross — that optimum sets the clock.

Sizing procedure: caps, clock, and ripple

A clean design walk-through for a target V_out, I_out, and ripple:

• 1. Pick the ratio N. Choose the smallest integer (or fractional) multiple that clears V_out with margin: N·V_in·η_headroom ≥ V_out. More stages than needed just burns efficiency.
• 2. Budget the droop. Decide allowable I·R_out sag (say 5% of V_out). That fixes the maximum R_out, hence the product f·C_fly ≥ 1/R_out(target). Example: V_out = 12 V, 5% = 0.6 V at I_out = 50 mA → R_out ≤ 12 Ω → f·C_fly ≥ 83 mF·Hz. At f = 500 kHz, C_fly ≥ 167 nF; round up to 220 nF or 330 nF X7R.
• 3. Size the reservoir C_out for ripple. Output ripple ΔV = I_out/(f·C_out). For 20 mV ripple at 50 mA and 500 kHz: C_out ≥ 50 mA/(0.5 MHz · 20 mV) = 5 µF. Watch ceramic DC-bias derating — an X7R 10 µF part can lose 60–80% of its capacitance at rated voltage; always size against the effective capacitance.
• 4. Check switch on-resistance. Keep the FSL term below the SSL term so frequency still buys you impedance: 2·R_on ≲ 1/(f·C_fly).
• 5. Verify voltage rating. Each capacitor and switch sees a specific node voltage — in a Dickson, stage k sits at ~k·V_in above ground. The top-stage cap and rectifier must be rated for the full V_out plus swing margin.

A crucial regime note: this holds while the pump is in the SSL and the caps fully settle each cycle. If f drops too low the output current collapses; if it climbs too high, gate-drive loss and incomplete charge transfer dominate.

Where charge pumps actually run: real hardware

Charge pumps are everywhere precisely because they need no magnetics and integrate onto silicon:

• NAND/NOR flash & EEPROM program/erase. Cells need ~15–20 V to tunnel electrons onto the floating gate (Fowler-Nordheim), generated on-die by multi-stage Dickson pumps at µA-to-mA loads. This is the single largest use of charge pumps by volume.
• Voltage inverters / RS-232 line drivers. The classic Maxim ICL7660 / MAX232: two 1 µF flying caps turn a single +5 V rail into ±5 V (or ±10 V) to meet the ±5 V minimum RS-232 line levels — no negative supply required.
• LCD / OLED bias and CCD/CMOS sensors, which need small, quiet ±V rails at low current where an inductor's EMI would corrupt the image.
• Gate-driver bootstrap supplies in half-bridges — a single bootstrap diode + cap is a one-stage pump that floats the high-side driver rail above the switch node.
• MEMS and piezo actuators, where 30–100 V at microamps is easiest to make with a stacked pump.
• Cockcroft-Walton descendants: CRT/tube EHT supplies, X-ray tubes, ion thrusters, and electrostatic precipitators reaching tens to hundreds of kV.

Representative parts: Skyworks/Peregrine adiabatic pumps, TI LM2662/TPS6040x, ADI ADP1613-class fractional pumps, and the on-die pumps inside every Micron/Kioxia/Samsung flash die.

Failure modes, limits, and best practice

The limits are as important as the equations:

• Current is the wall. To deliver more I_out you must raise f·C — but die area caps C, and f is bounded by switching loss. This is why charge pumps top out around a few hundred mA to ~1 A; above that, inductive converters win decisively.
• Ceramic DC-bias collapse. The most common field failure is an output that droops far worse than the datasheet predicts because the X7R flying/reservoir caps lost most of their capacitance under DC bias. Use C0G/NP0 where possible, over-size voltage rating (≥2× derating), and design against measured effective capacitance.
• Inrush and start-up. At power-on the output and flying caps are empty; the first cycles can slam huge peak currents through the switches. Good pumps use soft-start clocking or current limiting; without it you get switch damage or supply brownout (see inrush current limiting).
• Charge-injection & clock-feedthrough spikes. Non-overlapping (break-before-make) clocking is mandatory — if both switch phases conduct at once, you get shoot-through that shorts a charged cap and wrecks efficiency and EMI.
• Reverse leakage / droop under no clock. Stop the clock and the output decays through parasitic and load paths; pumps need continuous refresh, unlike an inductor that can freewheel.
• Thermal & lifetime: the ½C·ΔV² tax becomes I²R heating in the switches; keep junctions within rating, and remember electrolytic reservoir caps age (ESR rise) far faster than ceramics.

Best practice in one line: match the topology ratio to your actual V_out/V_in, size f·C for the droop budget, use non-overlapping clocks, and never trust nominal ceramic capacitance under DC bias.

Charge pump vs. inductor-based boost converter — when each wins

Attribute	Charge Pump (switched-cap)	Boost / Flyback (inductive)
Energy element	Capacitors (electric field)	Inductor / transformer (magnetic field)
On-die integration	Full — MIM/MOS caps, no magnetics	External inductor almost always needed
Voltage gain	Fixed ratios (2×, 3×, ½×) set by topology	Continuous, D-controlled up to ~5–8×
Efficiency at ratio-match	85–95% near ideal ratio; drops off fast otherwise	88–96% across wide range
Output current	µA to ~1 A (die-limited by cap size)	mA to tens of A
EMI / noise	Low radiated EMI, but charge-transfer spikes	Higher — di/dt ringing needs shielding