Synchronous Rectification: Replacing Diodes With Smart Switches

Why a Diode Drop Is a Tax You Can't Escape

A p-n or Schottky rectifier conducts when it is forward-biased, and the current-voltage relation is exponential: I = I_S·(e^(V/nV_T) − 1). The practical consequence is a nearly clamped forward voltage, V_F, in the 0.3–0.4 V range for a silicon Schottky and 0.6–0.7 V for a p-n junction, that barely moves as current climbs. The power burned is simply P = V_F·I, and because V_F is fixed, the loss scales linearly with load current and is independent of how good your heatsink is.

That linear tax becomes intolerable as output voltages fall. When rails migrated from 5 V to 3.3 V to 1.2 V to 0.8 V core voltages, the diode drop stopped being a small fraction of V_out and became a dominant one. A 0.45 V drop on a 12 V rail is a 3.75% efficiency hit; the same drop on a 1.2 V rail is a catastrophic 37.5% before you even count switching losses. This is the specific pressure that forced the industry to synchronous rectification.

• Governing loss (diode): P_D = V_F·I_avg + (½·Q_rr·V_R·f_sw) for reverse-recovery in p-n devices.
• The problem: V_F is set by band-gap physics, not by design — you cannot parallel your way out of it the way you can with resistance.
• The regime where it hurts: low V_out (≤5 V), high I_out (≥10 A), which is exactly the point-of-load and VRM space.

The Core Idea: Trade V_F for I²R

A power MOSFET in its ohmic (triode) region behaves like a voltage-controlled resistor. Below pinch-off the channel drop is V_DS = I_D·R_DS(on), and crucially this relation passes through the origin — at low current the drop is a few millivolts, not a fixed 0.4 V. Replace the rectifier diode with a MOSFET gated fully on during the interval the diode would have conducted, and the conduction loss transforms from a linear tax into a quadratic one you control:

• Diode: P = V_F·I
• Synchronous FET: P = I²·R_DS(on)

The break-even is where I·R_DS(on) = V_F, i.e. I = V_F/R_DS(on). For V_F = 0.45 V and R_DS(on) = 2 mΩ, break-even is 225 A per device — far above any practical current — so below that the FET always wins on conduction. There is a subtlety at the top end: because loss goes as I², at extreme currents the I²R term can eventually exceed a diode's linear V_F·I, but you defeat that by paralleling FETs, which divides R_DS(on) and therefore divides loss, something you cannot do with a diode's fixed drop.

A MOSFET also conducts bidirectionally when its channel is on — current can flow source-to-drain, not just drain-to-source. This is what makes it a valid rectifier substitute in a converter: during the freewheeling interval the inductor current flows 'backward' through the low-side switch, and an on channel carries it at low loss. When the gate is off, the intrinsic body diode still provides the rectifying path, which is both a safety net and a source of loss during dead time.

Timing Is Everything: Dead Time and Shoot-Through

In a synchronous buck, the high-side control FET (Q1) and the low-side synchronous FET (Q2) form a totem pole across the input rail. If both are on simultaneously — even for nanoseconds — you create a low-impedance short from V_in to ground called shoot-through. The peak current is limited only by parasitic resistance and can reach tens to hundreds of amps, spiking device temperature and, over cycles, causing catastrophic failure.

The mandatory defense is dead time (t_dead): a deliberate gap of typically 10–50 ns where both gates are low before either turns on. During this gap the inductor current has nowhere to go through a channel, so it forces the low-side FET's body diode into conduction at its full V_F ≈ 0.7 V (or an external Schottky in parallel at ~0.4 V). The dead-time conduction loss per switching period is:

• P_dead ≈ V_F(body)·I_L·(t_dead,rise + t_dead,fall)·f_sw
• Example: 0.7 V × 40 A × (30 ns) × 500 kHz ≈ 0.42 W — small, but it caps how short your dead time must be.

This creates the central trade-off: too much dead time wastes energy in the body diode and adds reverse-recovery loss; too little dead time risks shoot-through. Modern controllers use adaptive dead-time — sensing the switch-node voltage to close each gate only after the other has verifiably opened — to walk this line to a few nanoseconds. Some use predictive digital schemes that measure the diode conduction interval each cycle and shrink t_dead until body-diode conduction just disappears.

The Loss Budget: Sizing a Synchronous FET

Choosing the synchronous FET is an optimization, not a max-current lookup. The total loss in the low-side device is a sum of terms that pull R_DS(on) in opposite directions:

• Conduction: P_cond = I_rms²·R_DS(on)·D', where D' = 1 − D is the fraction of the period the SR conducts. Lower R_DS(on) helps here.
• Gate drive: P_gate = Q_g·V_gs·f_sw. A bigger FET (lower R_DS(on)) has a larger gate charge Q_g, so this term grows.
• Body-diode / dead-time: P_dead ≈ V_F·I_L·t_dead·f_sw as above, plus reverse-recovery Q_rr·V_in·f_sw.
• Output-capacitance (soft) switching: the SR turns on/off near zero volts in a buck, so switching loss is small — but C_oss must charge/discharge, giving ½·C_oss·V_in²·f_sw.

The right figure of merit is not R_DS(on) alone but the product R_DS(on)·Q_g (units of Ω·C ≈ V·s), because it captures the conduction-vs-gate-drive tension in one number. Trench silicon SR FETs reach ~15–40 mΩ·nC; GaN HEMTs push this an order of magnitude lower thanks to negligible reverse recovery and tiny gate charge. A practical sizing procedure:

• Set target: choose R_DS(on) so conduction loss is a chosen fraction (say 40%) of your loss budget at full load.
• Compute I_rms through the SR: for a buck, I_rms,SR ≈ I_out·√(1−D).
• Solve R_DS(on) ≤ P_budget,cond / (I_rms²·D').
• Verify P_gate = Q_g·V_gs·f_sw stays below its share at your switching frequency.
• Parallel devices if a single die can't hit the number — loss and thermals both divide, but Q_g and layout inductance add.

Remember R_DS(on) is strongly temperature-dependent: silicon rises roughly +0.4%/°C, so a device rated 2 mΩ at 25 °C is ~3 mΩ at 125 °C. Always size at the hot junction temperature, using the datasheet R_DS(on)(T_j) curve, or you will under-design by 40–50%.

Where the Gate Signal Comes From: Self-Driven vs. Controller-Driven

The synchronous FET needs a gate signal precisely phased to the converter. Two architectures dominate:

• Control-driven (complementary PWM): the same controller that drives the main switch generates a complementary gate for the SR, with programmed dead time. This is standard in synchronous buck converters and integrated VRMs, where both FETs share a driver IC (a 'DrMOS' or power stage). It gives precise timing and adaptive dead-time but requires a real controller and isolation on the secondary side of a transformer.
• Self-driven / self-synchronous: in transformer-isolated topologies (forward, LLC, active-clamp flyback), the SR gate is derived from a transformer winding or from sensing the FET's own V_DS. When the winding voltage flips to forward the diode, it also drives the gate on. Cheap and isolation-free, but timing tracks the transformer, not the load, so it struggles under light load and discontinuous conduction.

For isolated converters, dedicated SR controller ICs (e.g. devices in the TI UCC24612, Infineon, ON Semi families) sense the SR's drain-source voltage directly: when V_DS goes negative (body diode about to conduct) they turn the gate on within tens of nanoseconds, and they turn it off before current reverses by watching V_DS approach zero. The turn-off threshold is the critical spec — turn off too late in an LLC converter operating above resonance and the SR can conduct reverse current, dumping energy back and causing a hard-switching event on the primary. Typical detection thresholds are on the order of −5 mV to −20 mV for turn-on and a few mV for turn-off blanking.

Real Hardware, Real Numbers

Synchronous rectification is now baked into nearly every efficient DC-DC product:

• CPU/GPU VRMs (multiphase buck): a 12 V-to-0.9 V, 200 A regulator uses 6–16 phases, each an integrated power stage (e.g. Infineon/TI DrMOS at 5×5 mm) with a ~1.5 mΩ synchronous FET. Without SR the low-side diode loss alone would be 200 A × 0.4 V ≈ 80 W — nearly half the delivered power at 0.9 V. SR is not an optimization here; it is the only way the topology closes.
• USB-PD and laptop adapters (LLC / active-clamp flyback): 65–140 W adapters use secondary-side SR FETs (30–100 V rated, 5–20 mΩ) driven by SR controllers, lifting efficiency from ~88% to ~93–95% and eliminating the heatsink a Schottky would need. GaN primaries plus SR secondaries are how a 100 W charger fits in a pocket.
• Server 48 V bus converters: intermediate bus converters and 48 V-to-12 V LLC stages run SR at 500 kHz–1 MHz with GaN, hitting 97–98% peak efficiency because both conduction and switching losses are minimized.
• Point-of-load (POL) modules: the μModule / power-block products integrate both FETs, driver, and even the inductor; the datasheet efficiency curves that peak above 95% are entirely enabled by SR.

The device technologies map cleanly to voltage: trench silicon MOSFETs for ≤100 V secondaries, GaN HEMTs for 100–650 V where their zero reverse-recovery charge (no body diode) is decisive, and SiC MOSFETs for 650 V–1.7 kV in high-power SR applications. GaN's lack of a true body diode changes SR design: its 'reverse conduction' is a channel effect with a higher effective V_F (~2–3 V) during dead time, which actually penalizes long dead times and pushes designers to minimize t_dead aggressively.

Failure Modes, Limits, and Best Practice

Synchronous rectification adds active control to a formerly passive component, and that control is where things break:

• Shoot-through: the number-one failure. Caused by insufficient dead time, gate-driver Miller turn-on (the high dV/dt at the switch node couples through C_gd and re-turns-on the 'off' FET), or slow gate discharge. Defenses: adaptive dead time, low gate-drive impedance (strong pull-down), a negative gate-off bias, and choosing FETs with a high C_gs/C_gd (Miller) ratio.
• Body-diode reverse recovery: if the body diode conducts during dead time, its stored charge Q_rr must be swept out when the opposite FET turns on, causing a current spike and switching loss ≈ Q_rr·V_in·f_sw. Minimize dead time or use a parallel Schottky / a device with a fast body diode; GaN sidesteps this entirely (Q_rr = 0).
• Light-load reverse current: a synchronously rectified buck will happily sink current backward through the SR at light load (forced continuous conduction), wasting energy and even boosting V_in. The fix is diode emulation / DCM mode: the controller turns the SR off when inductor current crosses zero, mimicking a diode's blocking behavior to preserve light-load efficiency.
• Thermal runaway of R_DS(on): hotter silicon means higher R_DS(on) means more loss means hotter still. Size at T_j,max, verify the thermal path (R_θ,JA / R_θ,JC), and derate.
• Timing loss in resonant SR: in LLC/resonant converters the SR conduction window changes with frequency and load; a fixed-timing self-driven scheme mis-times and either leaves body-diode loss or forces reverse current. Use V_DS-sensing SR controllers with proper turn-off blanking.

Best-practice checklist: minimize gate-loop and power-loop parasitic inductance (tight layout, low ESL), use a driver with independent source/sink and negative off-bias for fast devices, verify dead time on the bench at full load and full temperature, add diode emulation for light-load efficiency, and choose the FET by the R_DS(on)·Q_g figure of merit at hot T_j — not by the headline 25 °C R_DS(on) number.

Diode rectification vs. synchronous rectification at a 1.2 V / 40 A output stage

Parameter	Schottky diode	Synchronous MOSFET	Consequence
Forward drop	V_F ≈ 0.45 V (fixed)	I·R_DS(on) ≈ 40 × 0.002 = 0.08 V	5–6× lower voltage drop
Conduction loss	V_F·I ≈ 0.45 × 40 = 18 W	I²·R_DS(on) ≈ 40² × 0.002 = 3.2 W	~15 W saved per rail
Loss vs. current	∝ I (linear)	∝ I² (quadratic)	SR wins hard at high I, loses at very high I
Control	Passive / self-commutating	Active gate + dead-time logic	Needs driver + timing; risk of shoot-through
Reverse blocking	Inherent	Body diode conducts if gate low	Enables synchronous operation but adds V_F·t_dead loss
Cost / complexity	1 component	FET + gate driver + control	Justified above ~10–20 A or below ~5 V