Analog Electronics

The SAR ADC: Digitizing a Signal One Bit at a Time

Inside a 16-bit SAR converter running at 1 MSPS, an internal comparator makes exactly 16 decisions in about 900 nanoseconds — each one a single binary question, "is the input above or below this trial voltage?" — and by the time the last question is answered, an analog voltage has been pinned down to one part in 65,536, roughly 76 microvolts on a 5-volt reference. No feedback loop, no oversampling, no exotic sampling clock: just a binary search executed in silicon at tens of megahertz.

That elegance is why the successive-approximation-register (SAR) ADC dominates the mid-speed, mid-to-high-resolution corner of data conversion — the workhorse behind industrial data acquisition, medical instrumentation, automotive sensing, and nearly every 12-to-18-bit converter you'll find in a modern microcontroller. It trades the raw throughput of a flash converter for a spectacular gain in efficiency, resolving N bits with a single comparator instead of 2ᴺ − 1 of them.

  • Core operationBinary search, N comparisons for N bits
  • LSB sizeQ = V_REF / 2ᴺ
  • Sweet spot8–18 bit, 100 kSPS–5 MSPS
  • Comparators1 (vs 2ᴺ−1 for flash)
  • DAC elementBinary-weighted cap array (CDAC)
  • Used inDAQ, medical, automotive, MCU on-chip ADCs

Interactive visualization

Press play, or step through manually. The visualization is yours to drive — try it before reading on.

Open visualization fullscreen ↗

Watch the 60-second explainer

A condensed visual walkthrough — narrated, captioned, under a minute.

The binary search: how a SAR converter thinks

A SAR ADC is a hardware implementation of the classic binary search. The signal is first frozen by a sample-and-hold (S/H) so it doesn't move during conversion, then the converter narrows a voltage range in half, N times, until it has located the input to within one least-significant bit (LSB).

The quantum step is set entirely by the reference and the resolution:

  • Q (LSB size) = V_REF / 2ᴺ. For a 12-bit converter on V_REF = 5 V, Q = 5 / 4096 ≈ 1.22 mV. At 16 bits, Q ≈ 76.3 µV; at 18 bits, ≈ 19.1 µV — well into the microvolt regime where board noise and thermal EMF start to matter.

The conversion proceeds MSB-first. On each step the successive-approximation register writes a trial code to an internal DAC, the DAC output V_DAC is compared to the held input V_IN, and the comparator's single-bit verdict decides whether that trial bit stays 1 or is cleared to 0:

  • Step 1 (MSB): Set bit N−1 → DAC outputs V_REF/2. If V_IN ≥ V_DAC, keep the bit (1); else clear it (0).
  • Step 2: Set bit N−2 → adds/holds V_REF/4. Compare, keep or clear.
  • Step k: Trial weight = V_REF / 2ᵏ. Each step halves the residual uncertainty.
  • Step N: After the LSB decision, the register holds the final code, latched as the output word.

Because each of the N decisions resolves exactly one bit, the total conversion always takes N comparison cycles — the defining efficiency of the architecture. A flash converter answers in one cycle but needs 2ᴺ − 1 comparators; the SAR answers in N cycles with just one.

The charge-redistribution DAC: where the bits actually live

The overwhelming majority of modern SAR converters build their internal DAC from a binary-weighted capacitor array — the charge-redistribution DAC (CDAC), first popularized by McCreary and Gray in 1975. Capacitors are used instead of resistors because in CMOS they are exceptionally well-matched, draw no static current, and naturally provide the sample-and-hold function for free.

The array holds N binary-weighted capacitors: C, C/2, C/4, … down to a terminating unit cap, summing to 2ᴺ unit capacitors (a 12-bit array is 4096 units of the smallest cap). Conversion runs in three phases governed by charge conservation, Q = C·V:

  • Sample: The top plates are tied to a common node, bottom plates to V_IN. Charge Q = C_total · V_IN is trapped on the array.
  • Hold: The top-plate switch opens, freezing the charge. This is the sample instant — the CDAC is the sampling capacitor.
  • Redistribute: Bottom plates are switched between GND and V_REF according to each trial bit. Charge redistribution drives the common node, and the comparator reads its sign relative to a threshold. This directly implements V_DAC = Σ bₖ · V_REF / 2ᴺ⁻ᵏ.

The huge practical advantage is zero static power: the CDAC only burns energy switching capacitors, so a SAR ADC's power scales almost linearly with sample rate. That is why on-chip SAR ADCs idle at microamps and why converters like the Texas Instruments ADS8881 (18-bit, 1 MSPS) or the Analog Devices AD7980 hit sub-milliwatt figures — energy-per-conversion in the tens of pJ range at lower resolutions.

Settling, timing, and the speed ceiling

The wall on SAR throughput is settling time. On every one of the N bit trials, the DAC node must settle to better than ½ LSB before the comparator is allowed to decide, or an early-bit error propagates as a large code error. Settling of the RC-driven CDAC node is exponential, and to reach ½-LSB accuracy at N bits you need roughly:

  • t_settle ≈ (N + 1) · ln(2) · τ ≈ 0.69·(N+1)·R_on·C, i.e. about (N+1) time constants. A 16-bit conversion needs its node to settle to ~11.8 τ — nearly 12 RC time constants — on each of 16 steps.

Total conversion time is the sum of the acquisition window plus N settled comparisons:

  • t_conv = t_acq + N · (t_settle + t_comp + t_logic)

This is why a 1 MSPS 16-bit part budgets on the order of 700–900 ns for the SAR phase and reserves the rest of the cycle for acquisition. Push the clock too fast and the MSB caps — which are the largest and slowest — haven't settled, so you buy speed with missing codes at the top of the transfer function.

Two design levers dominate:

  • R_on of the switches and unit-cap size set τ. Smaller caps settle faster and burn less energy, but shrink until kT/C noise (V_n,rms = √(kT/C)) sets a floor — halving C raises sampled noise by 3 dB. At room temperature a 1 pF cap gives ≈ 64 µV rms, already comparable to a 16-bit LSB.
  • Comparator regeneration time, which grows for small overdrives near the decision boundary (metastability), so high-speed SARs use dynamic latched comparators and sometimes redundancy to relax this.

Errors that define the datasheet: INL, DNL, and offset

SAR accuracy is ultimately a component-matching problem, because the transfer function is built from the ratios of capacitors. The two headline static specs are:

  • DNL (differential nonlinearity): the deviation of each code's actual width from one ideal LSB. If any code width goes below −1 LSB you get a missing code; a DNL error more negative than −1 LSB can also make the converter non-monotonic — deadly in a control loop where the ADC sits inside feedback.
  • INL (integral nonlinearity): the cumulative bow of the transfer function away from a straight line, dominated by the mismatch of the largest (MSB) capacitors. The worst DNL almost always occurs at the major carry transition (0111…1 → 1000…0), where the single biggest cap switches against the entire rest of the array.

Cap matching improves as √area, so achieving 16-bit-level INL from raw geometry alone demands impractically large arrays. Real converters therefore lean on:

  • Calibration: foreground or background trimming of the binary weights, storing correction coefficients to linearize INL.
  • Redundancy / non-binary weighting: using radix < 2 (e.g. 1.8-per-stage) so a wrong early decision can be recovered by later bits, which also relaxes MSB settling and boosts speed.

Dynamic specs — SNR, SINAD, ENOB, and SFDR — then tie it together. The quantization-noise ceiling is the familiar SNR = 6.02·N + 1.76 dB (98 dB ideal for 16 bits); real parts land a few dB below because comparator noise, kT/C, reference noise, and clock jitter all subtract. Aperture jitter t_j caps SNR at high input frequency via SNR_jitter = −20·log₁₀(2π·f_in·t_j) — at f_in = 100 kHz, 1 ns of jitter already limits you to ≈ 64 dB.

Sizing a SAR conversion: a worked design pass

Suppose you're digitizing a bridge-sensor front end: full-scale ±2.5 V differential, V_REF = 5 V, and you want 14 effective bits at 500 kSPS. A practical sizing pass:

  • Set the LSB. Q = 5 V / 2¹⁴ = 305 µV. Your input-referred noise (amplifier + ADC) must sit comfortably below this — target < ½ LSB ≈ 150 µV rms so quantization stays dominant.
  • Pick the sampling cap for noise. To get kT/C noise under ~90 µV rms you need C ≳ kT/V_n² ≈ (4.1×10⁻²¹)/(90×10⁻⁶)² ≈ 0.5 pF. Round up for margin; this also fixes the CDAC unit-cap floor.
  • Budget the timing. A 500 kSPS cycle is 2.0 µs. Allot ~600 ns for acquisition (driving the CDAC through the S/H) and ~1.4 µs for 14 settled bit trials → 100 ns per trial. With ~12 τ needed per settle, τ ≈ 8 ns, so R_on·C ≈ 8 ns — sets your switch sizing.
  • Drive the reference. The reference must recharge the switching array to ½-LSB within the trial time; this is a classic failure point (see below). A local 1–10 µF decoupling cap plus a low-output-impedance buffer is mandatory.
  • Drive the input. The ADC input is a switched-capacitor kickback load. Precede it with a wideband, low-distortion amplifier (a fully-differential driver such as the ADA4940 class) and an RC anti-alias / charge-reservoir filter, typically R ≈ 20–50 Ω and C ≈ 0.5–2 nF, sized so the amplifier settles the sampling glitch within the acquisition window.

The through-line: SAR design is a chain of settling and noise budgets, and the reference/input drivers usually limit the achievable ENOB long before the silicon does.

Where SAR ADCs win — and where they don't

The SAR owns the medium-speed, medium-to-high-resolution corner: roughly 8–18 bits at 100 kSPS to a few MSPS. Its killer features for system designers are single-cycle latency (no pipeline delay — critical inside digital control loops) and effortless multiplexing (each channel is fully converted before the mux moves on, with no memory of the previous channel).

  • Industrial data acquisition: 16/18-bit 1 MSPS parts (ADS8881, AD7982, LTC2378) behind multiplexed sensor banks.
  • Motor and power control: current/voltage sensing where the ADC sits in a PWM loop and low latency is non-negotiable.
  • Automotive & medical: ABS sensors, battery monitors, ECG/EEG front ends — SAR's determinism and low power fit safety-critical, low-drift needs.
  • On-chip MCU converters: nearly every 10/12-bit ADC in an STM32, PIC, or MSP430 is a SAR, because it's tiny, low-power, and needs no calibration DSP.

Where it loses: at very high speed, the N-cycle serial nature caps throughput, so radar and gigasample instrumentation use flash or pipelined converters (and interleaved-SAR arrays only push this so far). At very high resolution with low bandwidth — 24-bit weigh scales, precision temperature, audio — delta-sigma wins because oversampling and noise shaping beat raw component matching. The SAR is the pragmatic middle, and it's why it's the single most-produced ADC architecture on Earth.

SAR ADC versus the two neighboring architectures it competes against
AttributeSAR ADCFlash ADCDelta-Sigma (ΔΣ)
Resolution (typical)8–18 bit6–8 bit16–32 bit
Sample rate10 kSPS–10 MSPS1–56 GSPS1 SPS–5 MSPS
Latency1 cycle (no pipeline)1 cycleHigh (oversampled, decimated)
Comparators / conversion1 (used N times)2ᴺ − 11 (oversampled)
Best-fit applicationMultiplexed DAQ, control loopsRadar, oscilloscopes, wideband RFPrecision sensors, audio, weigh scales

Frequently asked questions

Why use a SAR ADC instead of a flash ADC?

A flash converter resolves N bits in a single cycle but needs 2ᴺ − 1 comparators, so it explodes in area and power — a 12-bit flash would need 4095 comparators and is essentially never built. A SAR uses one comparator N times, trading N cycles of latency for a roughly 2ᴺ-fold reduction in hardware. Choose flash only when you need gigasample bandwidth at low (6–8 bit) resolution; choose SAR for 12–18 bits at moderate speed.

What sets the maximum sample rate of a SAR ADC?

It's the sum of the acquisition window plus N settled comparison cycles. On every bit trial the internal CDAC must settle to better than ½ LSB — about (N+1) RC time constants — before the comparator decides, so total conversion time scales roughly with N times the array's RC settling. Push the clock past this and the large MSB capacitors don't settle, producing code errors at the top of the range.

What is charge redistribution and why capacitors instead of resistors?

Charge redistribution is the CDAC scheme where a binary-weighted capacitor array first samples the input as trapped charge (Q = C·V), then switches its bottom plates between V_REF and ground to synthesize each trial voltage by conservation of charge. Capacitors are used because CMOS caps match far better than resistors, draw zero static current, and provide the sample-and-hold for free — giving the SAR its hallmark near-zero idle power.

Where does the worst DNL error occur and why does it matter?

At the major carry transition (0111…1 → 1000…0), where the single largest MSB capacitor switches in against the sum of all the smaller caps — any mismatch there shows up directly as a wide or narrow code. If DNL drops below −1 LSB you get a missing code, and a non-monotonic converter inside a feedback loop can cause instability, which is why control-loop SARs specify guaranteed monotonicity.

How do you get 16- or 18-bit accuracy when capacitors only match so well?

Raw matching improves only as the square root of capacitor area, so brute-force geometry can't reach 16-bit INL economically. Modern high-resolution SARs add on-chip calibration (trimming the binary weights and storing correction coefficients) and often use non-binary/radix-under-2 redundancy so an early wrong decision can be corrected by later bits — which also relaxes MSB settling and buys speed.

Why does the reference driver so often limit real-world SAR performance?

Every bit trial dumps a switching transient onto the reference as capacitors are connected to V_REF, and that reference node must recover to within ½ LSB before the next comparison. If the reference source impedance is too high or its decoupling too small, the residual error corrupts later bits and shows up as INL and gain error. The fix is a local low-impedance buffer plus a 1–10 µF reservoir capacitor right at the ADC pin — it's the most common cause of a SAR under-performing its datasheet.