Sample and Hold: Freezing a Voltage Long Enough to Measure It

How it works: track, hold, and the two modes

A sample-and-hold has exactly two states, selected by a logic clock. In track (sample) mode the analog switch is closed and the hold capacitor C_H follows the input, charging through the switch's on-resistance Rₒₙ so that V_C = V_in with a settling time set by the RC time constant. When the clock commands hold, the switch snaps open in a few nanoseconds and C_H is left floating, ideally frozen at whatever voltage existed at the exact instant of opening — the aperture instant.

The canonical topology is a MOSFET or diode-bridge switch feeding C_H, buffered on both sides:

• An input buffer (a fast op-amp or open-loop transconductance stage) supplies the surge current I = C_H·dV/dt needed to charge C_H quickly without loading the source.
• The switch — typically a CMOS transmission gate, a JFET, or a Schottky diode bridge for the fastest parts — with Rₒₙ from a few ohms to a few hundred ohms.
• An output buffer with very high input impedance (a FET-input op-amp, input bias current in the pA range) so it reads C_H without discharging it.

The governing capacitor equation, I = C·dV/dt, appears twice and pulls in opposite directions: during acquisition you want large dV/dt, so you want small C_H; during hold you want dV/dt ≈ 0 from leakage, so you want large C_H. Every SHA design is a negotiation between those two lines.

The physics of the hold capacitor: droop and kT/C noise

Once the switch opens, the only thing keeping the answer honest is charge conservation on C_H. Any leakage current — the output buffer's input bias current, the switch's off-state leakage, dielectric absorption, PCB surface leakage — bleeds charge and the held voltage drifts. This is droop, and it is pure I = C·dV/dt rearranged:

• Droop rate dV/dt = I_leak / C_H. With a total leakage of 100 pA and C_H = 100 pF, dV/dt = 1 µV/µs. Hold that for a 1 µs conversion and you lose 1 µV — negligible at 16 bits on a 5 V range (1 LSB ≈ 76 µV). Shrink C_H to 10 pF and the same leakage gives 10 µV/µs.

The competing floor is kT/C sampling noise. When the switch opens, thermal noise in Rₒₙ is band-limited by C_H and sampled onto it, leaving an rms uncertainty independent of Rₒₙ:

• v_n(rms) = √(kT/C_H). At 300 K, k = 1.38×10⁻²³ J/K, so C_H = 1 pF gives 64 µV rms, 10 pF gives 20 µV, 100 pF gives 6.4 µV, and 1 nF gives 2 µV. To resolve 16 bits on 5 V (LSB = 76 µV) you need C_H roughly ≥ 10–100 pF just to keep quantization dominant over kT/C.

So both droop and noise argue for a bigger C_H, while acquisition speed and charge injection argue for a smaller one. The sweet spot for precision converters lands near 100 pF to 1 nF; for GHz track/holds it drops to a few hundred femtofarads, trading accuracy for bandwidth. Use a low-dielectric-absorption capacitor — C0G/NP0 ceramic, polypropylene, or silicon-on-die — never X7R or electrolytic, whose 'memory' effect reintroduces a fraction of the previous sample as a settling tail.

Charge injection, pedestal, and hold-mode feedthrough

The switch is not ideal. When a MOSFET turns off, the charge stored in its gate-channel and gate-drain overlap capacitance has to go somewhere, and part of it dumps onto C_H. This charge injection produces a hold pedestal — a step error at the moment of hold:

• ΔV_pedestal = Q_inj / C_H. A typical CMOS switch injects Q_inj ≈ 0.1–1 pC. Into 10 pF that is a 10–100 mV step; into 1 nF it is 0.1–1 mV. This alone can force C_H upward by an order of magnitude.

Because part of Q_inj is signal-dependent (the channel charge scales with V_GS), the pedestal is not a pure offset — it bends into gain and nonlinearity errors that show up as INL in the final ADC data. The standard countermeasures:

• Differential / balanced switching so injected charge is common-mode and cancels.
• Dummy switches and half-size compensation FETs that inject an equal-and-opposite charge.
• Bottom-plate sampling (open the ground-side switch first, before the signal-side switch) so the charge injected at the critical instant is signal-independent — the workhorse trick in every modern SAR and pipeline ADC.

A second parasitic is hold-mode feedthrough: the switch's off-capacitance C_off forms a divider with C_H, so a fraction C_off/(C_off+C_H) of the still-moving input leaks onto the held value. A 100 kHz, 2 Vpp input through C_off = 0.5 pF into C_H = 100 pF feeds through about 10 mV — often the dominant error at high input frequency, and another reason to keep C_H reasonably large and layout parasitics tiny.

Aperture time and aperture jitter: the timing that sets ENOB

The single most underappreciated spec is aperture jitter — the random cycle-to-cycle uncertainty in when the switch actually opens. If the input is slewing at dV/dt, a timing uncertainty δt turns directly into a voltage error δV = (dV/dt)·δt. For a sine wave of amplitude A and frequency f_in, the worst-case slew is dV/dt = 2πf_in·A at the zero crossing, so the rms error is:

• V_error(rms) = 2π·f_in·A·t_jitter(rms). Normalizing to a full-scale sine, the jitter-limited SNR is SNR = 20·log₁₀[1/(2π·f_in·t_j)] dB.

Run the numbers and the tyranny of jitter is obvious. To reach 12 effective bits (SNR ≈ 74 dB) at f_in = 100 MHz you need t_j ≤ 0.3 ps rms. At f_in = 1 GHz you need well under 0.1 ps — which is why RF sampling converters obsess over clock phase-noise, not just the SHA silicon. Two related definitions matter:

• Aperture delay t_ap: the fixed lag between the clock edge and the actual sampling instant (tens of ps to a few ns). A constant delay is harmless — it just shifts the sample time — but its variation is jitter.
• Aperture (sampling) bandwidth: the effective input bandwidth of the track path when in sample mode, which must exceed the highest input frequency you intend to undersample.

Practically, jitter budget is split between the clock source (a low-phase-noise crystal or PLL) and the internal aperture jitter of the converter. Undersampling a 200 MHz IF onto a 20 MSPS converter is legal precisely because the SHA's aperture bandwidth is far higher than its sample rate — the hold capacitor freezes the RF, and the low-rate back-end digitizes the frozen value at leisure.

Sizing procedure: from spec to component values

Designing (or specifying) an SHA is a bounded optimization. A clean procedure:

• Step 1 — Set the noise floor. Pick C_H so that √(kT/C_H) is comfortably below ½ LSB. For 14-bit on 5 V (LSB ≈ 305 µV), even 10 pF (20 µV) is fine; for 18-bit on 5 V (LSB ≈ 19 µV) you need ~100 pF–1 nF.
• Step 2 — Bound droop. Require dV/dt·t_hold < ½ LSB. With t_hold = 1 µs and I_leak = 100 pA, solve C_H > I_leak·t_hold/(½ LSB). This usually confirms or raises the Step-1 value.
• Step 3 — Bound the pedestal. ΔV = Q_inj/C_H should be within your calibration/cancellation budget; if not, add bottom-plate sampling or increase C_H.
• Step 4 — Check acquisition time. t_acq ≈ N·τ = N·Rₒₙ·C_H, where N ≈ ln(2^bits) — about 9τ for 0.01% (14-bit) settling, 11τ for 16-bit. With Rₒₙ = 50 Ω and C_H = 100 pF, τ = 5 ns, so 16-bit acquisition ≈ 55 ns, capping the sample rate around 10–15 MSPS. If too slow, lower Rₒₙ (bigger switch — but more Q_inj) or C_H (more noise). This is the central loop.
• Step 5 — Size the input buffer. Peak charge current is I = C_H·(dV/dt) = C_H·SR. For a 2 V step acquired in 20 ns, dV/dt = 100 V/µs; into 100 pF that is 10 mA of slew current the buffer must source without clipping.
• Step 6 — Allocate the jitter budget from the target SNR at max f_in using SNR = 20·log₁₀[1/(2πf_in t_j)], then choose clock and SHA accordingly.

The tension is always the same triangle: speed (small C_H, small Rₒₙ) vs. accuracy (large C_H) vs. droop/noise (large C_H). Modern integrated converters resolve it by shrinking C_H to a few hundred fF and burying the switch on-die where parasitics and jitter are minimized.

Real hardware and applications

Discrete SHAs still exist, but the technology's real footprint is inside nearly every data converter. Notable and representative parts and uses:

• Classic monolithic SHAs: the AD783 (250 ns acquisition, low droop) and the fast AD9101/HA-5330 track/holds — the reference designs that taught a generation the pedestal-vs-droop trade-off.
• On-chip in SAR ADCs: every successive-approximation converter integrates its sampling capacitor as the DAC (charge-redistribution architecture) — the hold capacitor and the conversion element are literally the same array, with bottom-plate sampling for linearity.
• Pipeline and RF-sampling ADCs: a front-end track/hold with sub-picosecond aperture jitter feeds GSPS pipelines (e.g. multi-GSPS RF ADCs) used in 5G base stations and software-defined radio, directly sampling hundreds of MHz of IF.
• Peak detectors and analog memory: particle-physics detectors and CCD/CMOS image sensors use switched-capacitor sample-and-hold cells (correlated double sampling) to capture a reset level and a signal level, subtracting kTC and 1/f noise.
• DAC deglitchers: a hold on the DAC output masks code-transition glitches, so the SHA runs 'after' the converter as well as before it.

Wherever a fast, moving analog quantity must be measured by a slower or serial process — a rotor-position resolver, a per-cell battery voltage during a scan, a lidar return pulse — a sample-and-hold is the element that stops time long enough to look.

Failure modes, limits, and best practice

SHAs fail in specific, diagnosable ways, and the layout matters as much as the silicon:

• Excess droop from leakage: usually PCB surface contamination or flux between the C_H node and ground/supply. Guard-ring the hold node, drive the guard at the same potential, and clean the board — a fingerprint can leak nanoamps.
• Dielectric absorption tail: using X7R or tantalum for C_H makes the output creep back toward the previous value with a millisecond time constant, producing hysteresis-like INL. Fix: C0G/NP0, polypropylene, or Teflon.
• Pedestal drift with temperature: Q_inj varies with temperature and common-mode, so a nulled pedestal reappears over the operating range. Use differential switching or bottom-plate sampling rather than a one-point trim.
• Jitter-limited SNR ceiling: if measured SNR is flat with input amplitude but degrades with input frequency at 6 dB per octave-doubling of f_in, you are jitter-limited — no better SHA silicon will help; clean up the sample clock.
• Insufficient acquisition (undersettling): too little track time leaves the previous sample partially present — memory/inter-symbol error. Always allow ≥9–11 time constants; verify with a full-scale step, not a slow ramp.
• Hold-mode feedthrough at high f_in from switch C_off: keep C_H large enough, minimize trace parasitics, and route the input away from the held node.

Best practice, distilled: choose C_H by the noise/droop floor, defend it with guarding and a low-DA dielectric, kill signal-dependent charge injection with bottom-plate/differential sampling, budget the aperture jitter against your highest input frequency, and always validate acquisition with a worst-case full-scale step at the real sample rate.

Sample-and-hold design trade-off: choosing the hold capacitor C_H

Parameter	Small C_H (10 pF)	Large C_H (1 nF)	Governing relation
Acquisition time (settling to 0.01%)	Fast (~9τ, tens of ns)	Slow (~9τ, µs)	t_acq ≈ 9·Rₒₙ·C_H
Droop rate	High (e.g. 10 mV/µs)	Low (e.g. 0.1 mV/µs)	dV/dt = I_leak/C_H
Charge-injection pedestal	Large (mV)	Small (µV)	ΔV = Q_inj/C_H
kT/C sampling noise (rms)	High (~20 µV at 10 pF)	Low (~2 µV at 1 nF)	v_n = √(kT/C_H)
Best fit	High-speed track/hold	High-resolution, slow ADC	Bandwidth vs. accuracy